1. Field of the Invention
Embodiments of the invention generally relate to integrated circuits. In particular, embodiments of the invention relate to memory circuits.
2. Description of the Related Art
Semiconductor memory devices are ubiquitous in digital electronics devices. Examples of these devices include computers, cameras, digital media players, games, personal digital assistants, mobile phones, navigation devices, non-volatile storage products, and the like. Examples of non-volatile storage products include CompactFlash (CF) cards, MultiMedia cards (MMC), secure digital (SD) cards, Flash PC cards (e.g., ATA Flash cards), SmartMedia cards, solid-state disks (SSDs), hybrid hard drives, and memory sticks. Semiconductor memory provides storage and retrieval of data.
There exist many types of semiconductor memories. Examples of memories include various types of random access memory (RAM) (including SRAM, DRAM, and SDRAM), flash memory, electrically erasable programmable read only memory (EEPROM), magnetoresistive random access memory (MRAM), programmable conductor memory, ferroelectric memory, and the like. There are also many subtypes within these memories.
Typically, the memory cells of a memory device are arranged in one or more arrays and are accessed by activation of appropriate word lines (rows) and bit lines (columns). In most types of memory devices, each cell stores a single bit of data. However, some cells, such as flash memory cells, can store data in more than one level (more than one bit per cell).
Memory devices can also be organized into pages and further into blocks. For example, NAND flash is generally organized into blocks and pages. This organization can also be found in NOR flash, electrically erasable programmable read only memory (EEPROM), and programmable read only memory (PROM). The sizes of the blocks and pages can vary in a very broad range. One example of a 2 gigabyte (GB) memory array has 2,048 blocks, each block having 64 pages, with each page having 2,112 bytes, including 2,048 data bytes and 64 spare bytes (not including spare blocks, pages, rows, columns, etc.). Conceptually, this is illustrated in FIG. 1.
Bad or unusable memory cells can be identified during test. For example, a memory cell can fail for being stuck in a particular logic state, for not meeting a timing specification, or the like. During production, these failures can be mapped and corrected by substitution of defective rows and/or columns with extra or redundant rows and/or columns in an array. This type of failure is typically handled by the permanent mapping of internal addresses for individual rows and addresses within an array and is transparent to the end user.
Cells can also fail in the field. For example, many non-volatile memory types can wear out over multiple write cycles. Some memory devices can also include error correction codes (ECC), and are tolerant of bad cells within correctable limits. Unless correctable by some form of error correction, bad or unusable memory cells should not be used. Bad or unusable memory cells can affect the usability of higher order memory units. For example, bad cells can cause a row to be unusable, and the page(s) of the row to be unusable. Blocks of memory can also have spare pages to replace bad pages. When an insufficient number of pages for a block is available, the entire block may be marked as a bad block, and none of the pages of that block are typically accessible.
A problem arises in the handling of bad blocks. Bad blocks can be marked in a bad block table. For example, if a block is determined to be bad during production test, a repair procedure can be used to replace the bad block with a spare block.
With reference to FIG. 2, in one example, two or more arrays store data from or provide data to a data bus. It can take longer to write to or read from a page of data to or from an array 202, 204 than to or from a cache register 206, 208. For speed, the memories can be arranged such that a page from one array 202 is written to or read first, then a page from a second array 204 is written to or read, then a new page is written to or read from the first array 202, and so forth. This is known as “ping-ponging,” and is fast because the data from the alternate array can be preloaded into the applicable cache register 206, 208 while the data from the other cache is being written or read. Other registers 210, 212 can assist with the writing or the fetching of data. If the arrays 202, 204 are on the same chip, the cache registers 206, 208 can be shared, i.e., there would typically be only one cache register.
However, if the addresses are not sequential, then the preloading may not occur efficiently. For example, when two 8-bit chips are used to provide data, then address lines that are provided to the two chips are typically shared, and the least significant bit (LSB) of an address line is redundant. In a conventional chip with multiple arrays, not only are the address lines shared, but a row decoder is also typically shared among the multiple arrays. When a block of an array is bad, a repair solution can map a different block to the same logical address as a good block. However, the activation of a different set of row lines for the replacement block can considerably lengthen write or read times because, for example, two different physical memory locations are then accessed from within the memory device for writing or reading. This is shown in FIG. 3.
FIG. 3 illustrates an example of a conventional technique for pairing blocks from two different memory arrays 302, 304. More than two memory arrays can be “paired” or matched, i.e., associated for storage and retrieval together. In another example, 4 arrays or 8 arrays are “paired.” In the illustrated example, the first four blocks (1A-4A) 306, 308, 310, 312 from memory array A 302 are good. A first block 1B 314, a second block 2B 316, and a fourth block 4B 320 from memory array B 304 are good. However, a third block 3B 318 of memory array B 304 is bad. The first block 1A 306 and the first block 1B 314 are paired. The second block 2A 308 and the second block 2B 316 are paired. The fourth block 4A 312 and the fourth block 4B 320 are paired.
However, the third block 3A 310 from array A 302 is not paired with the third block 3B 318 from array B 304 because the third block 3B 318 is bad and is not usable. Rather, the third block 3A 310 is paired with another block XB 322 from array B. Typically, the good blocks at the end (by physical address) of an array are spare blocks, and the other block XB 322 that is used is selected from one of the spare blocks. For example, block XB 322 can be the 2,050-th block of an array specified to have at least 2,048 good blocks. The third block 3A 310 and the other block XB 322 are at different physical addresses, and when pages of data are stored to or retrieved from each, the pages from the third block 3A 310 and the pages from the block XB 322 are internally accessed using two separate accesses and without “ping-ponging.” This reduces performance. For example, the technique illustrated in FIG. 3 typically uses some form of internal controller intervention to select the replacement block(s) and to combine data from separate internal memory reads, which further slows down access.
The use of multiple arrays for data is common. In systems with multiple channels of data, there can be data from multiple arrays for a data stream. Another example where blocks can be paired is when a data bus is relatively wide, such as in a 32-bit wide data bus, and each of four memory arrays handles 8 bits of the 32 bits of data.
FIG. 4 illustrates an example of a conventional technique for pairing blocks from two different memory arrays 402, 404. In this technique, the entire physical address of a bad block is skipped, and the next physical address with two or more good blocks is used. This technique still typically uses controller intervention to manage the jump in physical addresses. In the illustrated example, the first four blocks (1A-4A) 406, 408, 410, 412 from memory array A 402 are good. A first block 1B 414, a second block 2B 416, and a fourth block 4B 420 from memory array B 404 are good. However, a third block 3B 418 of memory array B 404 is bad. The first block 1A 406 and the first block 1B 414 are paired. The second block 2A 408 and the second block 2B 416 are paired. The fourth block 4A 412 and the fourth block 4B 420 are paired.
However, the third block 3A 410 from array A 402 is not paired with the third block 3B 418 from array B 404 because the third block 3B 418 is bad and is not usable. In contrast to the example of FIG. 3, where the block 3A 310 is still used, in the example of FIG. 4, the third block 3A 410, while good, is left unpaired and unused. This preserves the ability of the arrays 402, 404 to “ping-pong” for speed when reading the various pages of associated blocks as the paired blocks arranged in this manner use the same physical addresses and are accessible with activation of the same rows of a shared row decoder. However, the third block 3A 410 is not utilized despite its viability and is effectively treated as a bad block. This decreases the number of available blocks for an array, and if the effective number of good blocks falls below the minimum specified, this can decrease the production yield and increase the cost of production.